Course: Resolved signals and types with resolution functions in VHDL
Learn how the std_logic type handles driver conflicts internally. See how to implement custom data types with resolution functions for multiple drivers.
Showing 13–24 of 53 results
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Course: IoT and FPGAs: Building a cloud-connected VHDL design
Bring your VHDL project online. Set up a neat GUI dashboard using the Blynk IoT platform and a Raspberry Pi and send over-the-air (OTA) updates to your FPGA.
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Course: Cocotb introduction
Write testbenches in Python for your VHDL design with the Cocotb hardware verification framework. Learn to use Python’s asynchronous constructs in the Questa and GHDL simulators.
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Course: RISC-V processor Hello World! in VHDL
Create a reduced instruction set computer using the RISC-V processor architecture. Learn how a CPU works by implementing one in VHDL and running it on the FPGA.
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Course: MicroBlaze SoC design
$59Learn how to build a system-on-chip (SoC) design by using a MicroBlaze soft-core processor, existing IP cores, and custom VHDL modules.
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Course: I²S audio codec ADC/DAC interface using VHDL and the Xilinx Zynq FPGA
Learn to implement the I²S protocol in VHDL and configure the ADAU1761 ADC/DAC audio codec chip on the Xilinx Zedboard with bare-metal C programming.
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Course: I²C controller for interfacing a real-time clock/calendar module in VHDL
$59Learn to create an I²C controller (master) in VHDL and communicate with the Digilent Pmod RTCC: Real-time Clock / Calendar module.
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Course: SPI master for reading ambient light sensor
$59Learn to create an SPI master in VHDL for reading an ambient light sensor from an FPGA. We also make an SPI slave BFM for simulating the ADC chip.
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Course: Combining VHDL frameworks: VUnit, UVVM, and OSVVM
You don’t have to use only one VHDL verification framework. We can pick and choose the features we need and combine them to create awesome testbenches.
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Course: VUnit for structured testbench and advanced BFM design
$59Learn to create neat testbenches and verification components using this testing framework’s VHDL libraries. Automate your simulation flow with VUnit’s Python test runner.
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Course: UVVM introduction
The Universal VHDL Verification Methodology (UVVM) framework provides a utility library, reusable verification components, and a way to structure your VHDL testbenches.
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Course: Advanced BFM signaling and transaction-based TB
Build a testbench that separates bit-level logic into separate modules and uses a command interface to control executor processes.
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