The most common type used in VHDL is the std_logic. Think of this type as a single bit, the digital information carried by a single physical wire. The std_logic gives us a more fine-grained control over the resources in our design than the integer type, which we have been using in the previous tutorials.
Normally, we want a wire in a digital interface to have either the value ‘1’ or ‘0’. These two values are the only values that a bit,