I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.
Similar Posts
How to create a breathing LED effect using a sine wave stored in block RAM
I’ve noticed that many of the gadgets that I’ve bought the last couple of years have shifted away from LED blinking to led breathing. Most electronic gizmos contain a status LED whose behavior gives away indications of what’s going on inside of the device. My electric toothbrush flashes an LED when it’s time to recharge…
Why you always need a testbench
As most hardware engineers, I started off my computer science career by learning a sequential programming language. The first language I learned at the University of Oslo was Java. While it’s not considered to be the most exciting language today, at the time, Java was at the pinnacle of its popularity. The engineers who built…
How to create your first VHDL program: Hello World!
When learning a new programming language, I always like to start by learning how to print. When you master outputting “Hello World!”, you know that you’ve got the environment working. It also shows you the basic skeleton of the language, the bare minimum code required to produce any output. You might be thinking: but VHDL…
How to initialize RAM from file using TEXTIO
A convenient way to populate block RAM with initial values is to read binary or hexadecimal literals from an ASCII file. This is also a good way to create a ROM (read-only memory) in VHDL. After all, RAM and ROM are the same thing in FPGAs, ROM is a RAM that you only read from….
How to use constants and Generic Map in VHDL
Creating modules is a great way to reuse code, but often you need the same module with smaller variations throughout your design. This is what generics and the generic map are for. It allows you to make certain parts of the module configurable at compile-time. Constants are used when we want to avoid typing the…
How to create a signal vector in VHDL: std_logic_vector
The std_logic_vector type can be used for creating signal buses in VHDL. The std_logic is the most commonly used type in VHDL, and the std_logic_vector is the array version of it. While the std_logic is great for modeling the value that can be carried by a single wire, it’s not very practical for implementing collections…
First of all, thank you so very much!
These are by far the most comprehensible tutorials I have come across like ever!
Brilliant work.
So here my two cents out of gratitude:
Basic VHDL Quiz – part 4
Which statement is not true?
Answer 3 : The return statement cannot be omitted.
-> Correct
So the return statement CAN be omitted???
“Unlike in most other programming languages, the return keyword is mandatory in functions in VHDL.”
Confused by double negation. Me or you 😉
Good catch! I’ve changed the answer now. I was trying to make you think, but in the process I confused myself too 🙂
“The return-keyword cannot be used in a procedure”. I believe that this is incorrect, e.g.
https://web.archive.org/web/20200629023040/http://vhdl.renerta.com:80/source/vhd00060.htm
It is true, of course, that you cannot return a value with it, that’s the only (?) difference between procedures and functions. But, as in other languages, you can use “return” as control flow statement to “force an exit”.
You are right! I missed the possibility of using return statements in procedures without returning a value. According to the Renata link you posted, functions must return a value, while procedures can have return statements, but then without a return value.
I am changing this question.