STD_LOGIC_TEXTIO package declaration

Compatibility aliases that forward to the textio procedures defined in STD_LOGIC_1164.

Use clause: library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
Source: ieee/std_logic_textio.vhdl in the IEEE 1076 OSR, tag 1076-2019
Apache License 2.0, © 2019 IEEE P1076 WG Authors
Length: 62 lines
VHDL revisions: Standardised in 1076-2008; carried forward through 1076-2019

Overview

STD_LOGIC_TEXTIO is a thin compatibility package: every declaration in it is an alias that points back to one of the READ, WRITE, HREAD, HWRITE, OREAD, or OWRITE procedures defined in STD_LOGIC_1164. No new behaviour is introduced.

Per §16.7 of IEEE Std 1076-2019, the package exists to replace the non-standard STD_LOGIC_TEXTIO implementations that vendors shipped with pre-2008 versions of the standard. New designs should use the procedures in STD_LOGIC_1164 directly; this package is here so legacy code that imports IEEE.STD_LOGIC_TEXTIO still compiles against the current standard. There is no body - the aliases resolve directly to the original subprograms.

What's defined here

Aliases: READ (4 signatures), WRITE (2 signatures), HREAD (2 signatures), HWRITE, OREAD (2 signatures), OWRITE. All forward to the matching procedures in IEEE.std_logic_1164.
Types: None. The package depends on STD.TEXTIO.LINE, SIDE, WIDTH and the STD_ULOGIC / STD_ULOGIC_VECTOR types from STD_LOGIC_1164.

VHDL source listing

doc

File header Comment block (40 lines)

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-- -----------------------------------------------------------------
-- 
-- Copyright 2019 IEEE P1076 WG Authors
-- 
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
-- 
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
-- 
--     http://www.apache.org/licenses/LICENSE-2.0
-- 
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied.  See the License for the specific language governing
-- permissions and limitations under the License.
--
--   Title     :  Standard multivalue logic package
--             :  (STD_LOGIC_TEXTIO package declaration)
--             :
--   Library   :  This package shall be compiled into a library
--             :  symbolically named IEEE.
--             :
--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
--             :
--   Purpose   :  This packages is provided as a replacement for non-standard
--             :  implementations of the package provided by implementers of
--             :  previous versions of this standard. The declarations that
--             :  appeared in those non-standard implementations appear in the
--             :  package STD_LOGIC_1164 in this standard.
--             :
--   Note      :  No declarations or definitions shall be included in,
--             :  or excluded from this package.
--             :
-- --------------------------------------------------------------------
-- $Revision: 1305 $
-- $Date: 2008-06-27 14:28:49 +0930 (Fri, 27 Jun 2008) $
-- --------------------------------------------------------------------

use STD.TEXTIO.all;
library IEEE;
use IEEE.std_logic_1164.all;

PACKAGE std_logic_textio IS

  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC];
  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC, BOOLEAN];
  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR];
  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
  alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC, SIDE, WIDTH];
  alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];

  alias HREAD  is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR];
  alias HREAD  is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
  alias HWRITE is IEEE.std_logic_1164.HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];

  alias OREAD  is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR];
  alias OREAD  is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
  alias OWRITE is IEEE.std_logic_1164.OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];

END PACKAGE std_logic_textio;