Digital filters in FPGAs

This article is by guest author Dimitar Marinov, whom I (Jonas) got in touch with after seeing his excellent videos about DSP filters. You can read more about Dimitry and find a link to his YouTube channel below the blog post. But first, read on to learn about FIR and IIR filters and the difference between the two.

This article is part of a series. Click here to read Dimitar’s other articles:

Introduction

If you’re an HDL developer, chances are you’re going to encounter digital filters in some shape or form throughout your career. Hence this blog post serves as an introduction to the topic, seen from the eyes of a hardware developer.

This article discusses mainly the implementation of the filters rather than the theory and design. Therefore, it would be beneficial to have some basic understanding of the digital signal processing theory. If not, please refer to your favorite DSP book; mine is [1] 🙂.

FIR and IIR filter types

Digital filters are devices that modify the spectrum and phase of an input signal. Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) are the two main types of digital filters you’re most likely to work with. Both are quite different from each other, yet they can be used interchangeably (in some situations).

The main difference between the two when it comes to implementation, however, is the signal path – FIRs are feed-forward-based (there are exceptions[1]), whereas IIR filters are based on a combination of feed-forward and feedback paths. This difference brings unique challenges when it comes to HDL implementation.

FIR filter block diagram
Figure 1 (a): FIR filter block diagram
Figure 1 (b): IIR filter block diagram

Filter building blocks

Figure 1 shows examples of FIR and IIR filter structures. The block diagrams specify the signal path and its operations, but not how they are implemented. Notice that both devices are composed of three main components – addition (the circles), multiplication (the triangles), and memory elements (the squares).

Memory elements

These are memory storage units that hold z-amount of consecutive data samples. For example, a delay element of z-1 holds one value, whereas z-N holds N-amount of values. When there are multiple delay elements in a row, the data is being shifted (transferred) from one element to the next once per sampling period. All memory elements connected sequentially form a delay line.

Arithmetic operators

The most common arithmetic operations involved in digital filters are addition and multiplication, with each using its own hardware. They are so common that some hardware allows them to perform a multiply-add operation, where both operations are performed at once. There are, of course, other operations such as division, logarithmic and trigonometric operations, but they are far less common.

Sampling rate

This is the rate at which the data is being processed by the filter, also known as sampling frequency or sampling clock/period (Fs). During this period, all operations (memory or arithmetic) are executed once.

Part 2: Finite Impulse Response Filters

Click here to view the follow-up article about FIR filters implemented using VHDL:
Part 2: Finite Impulse Response Filters

References

  • [1] Richard G. Lyons, “11.5 Filtering Aspects of Time-Domain Averaging” in Understanding Digital Signal Processing

My name is Dimitar Marinov. I started doing electronics in high school, so I decided to make it my vocation. So I joined the Electronics Design Engineering (EDE) course at Aarhus Univerity in Denmark (2012-2016), where I discovered DSP and FPGAs.

Afterward, I joined a company in Hamburg, Germany, called Ibeo Automotive System (2017-2019), where I developed FPGA firmware for LIDAR sensors.

Later I took a Master's course in Electronic Communication and Computer Engineering (ECCE) at the University of Nottingham (2019-2020) and then joined a small company in Edinburgh called Photon Force (2020-2021) where I did FPGA design for high-speed cameras.

In late 2020 I decided to start a YouTube channel dedicated mainly to FPGAs. However, on this platform, I'll be sharing posts and ideas that are better presented in written form.

Similar Posts

Formal verification in VHDL using PSL

Formal verification in VHDL using PSL

ByMichael Finn Jørgensen

When designing VHDL for safety-critical FPGA applications, it’s not enough to write testbenches at best-effort. You have to present proof that the module works as intended and without undesirable side-effects. Formal verification techniques can help you map a requirement to a test, proving that your VHDL module conforms to the specification. It’s an instrumental tool…

FIR FIlter Testing

Part 4: FIR filter testing

ByDimitar Marinov

So far, the spotlight has fallen over the FIR filter design and its various forms. However, there is a problem that is just as important – how to ensure the implementation is working correctly. Whereas there are some standard techniques, it’s not always clear whether the design is error-proof. Therefore, this post discusses the most essential testing procedures and introduces a verification method that can easily incorporate them.

List of four text strings on paper

How to create a list of strings in VHDL

ByJonas Julian Jensen

Text strings in VHDL are generally limited to fixed-length character arrays. That makes sense because VHDL describes hardware, and generic-length strings require dynamic memory. To define an array of strings, you have to allocate space at compile-time for the highest number of strings you want to store. Even worse, you must decide on the strings’…

3 Comments

  2. I need to implement iir chebyshev 1 lowpass filter on fpga, order 6 , i need vhdl code for help , im using direct form 1 .

    Reply

Leave a Reply

Your email address will not be published. Required fields are marked *