Short-circuit operations in VHDL
A binary operator is an operator that takes exactly two arguments. Examples of such are addition or multiplication and, of course, the familiar Boolean logical operators we use in VHDL: and, or nand nor xor and xnor.
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Operator precedence in VHDL
VHDL groups operators into classes with different precedence levels. Operators are evaluated according to their classes, starting with the highest level. Operators of the same class don’t have any predefined priority. Instead, they are evaluated left to right in the order they appear in the code.
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How to define and print multiline string literals in VHDL
This article shows how to work with strings containing line breaks in VHDL. Read on to learn how to split long lines in your VHDL code, print text containing newline characters, and how VHDL differs from regular programming languages regarding non-printing control characters in strings.
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Part 3: FIR filter types
The previously discussed filter describes a general-purpose device that can fit in many applications but is not necessarily the optimal solution. This is where application-specific FIR structures come in. Therefore, this post aims to present some of the more popular filter structures used in specialized applications.
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Part 2: Finite impulse response (FIR) filters
As an FPGA designer, you have the freedom to implement the (finite impulse response) FIR filter either parallel or in series. Read the article to find out how to implement a FIR filter using VHDL!
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Part 1: Digital filters in FPGAs
Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) are the two types of digital filters you’re most likely to use in FPGAs. This article discusses the implementation of the filters seen from the eyes of a hardware developer.
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Using the ‘stable and ‘quiet attributes in VHDL
The ‘stable and ‘quiet attributes are predefined in the VHDL standard and work on signal objects. We can use these special features in simulation to check that a signal’s value remains untouched for a given period.
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How to link Quartus Prime IP libraries to VUnit
Have you ever wanted to run a VHDL simulation that includes a Quartus IP core through the VUnit verification framework?
This tutorial shows you how to generate, incorporate, and link external Quartus IP libraries to VUnit.
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The ModelSim commands you need to know
Many people struggle to understand the ModelSim/QuestaSim VHDL simulator’s workflow. I think that’s unnecessary because the basic workflow isn’t hard to learn. I regard the graphical user interface (GUI) as a front-end for the commands listed in this article. For example, when you click the Compile button in the ModelSim GUI, it runs the vcom…
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Getting started with VUnit
VUnit is one of the most popular open-source VHDL verification frameworks available today. It combines a Python test suite runner with a dedicated VHDL library to automate your testbenches.
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