Most VHDL simulators use the Tool Command Language (Tcl) as their scripting language. When you type a command in the console of the simulator, you are using Tcl. Furthermore, you can create scripts with Tcl that run in the simulator and interact with your VHDL code.
In this article, we will create a self-checking testbench that used Tcl instead of VHDL to verify that a VHDL module behaves correctly.
How do you stop the VHDL simulator when the simulation is complete? There are several ways to do that. In this article, we will examine the most common ways to end a successful testbench run.
The VHDL code presented here is universal, and it should work in any capable VHDL simulator. For the methods involving Tcl, I will list the commands for the ModelSim and Vivado simulators.
You can download an example project with the four different testbenches from this article if you have ModelSim installed.
When you have worked with VHDL code written by many other FPGA engineers, you are bound to notice that there are two common ways to model an edge detector in VHDL. There’s the rising_edge(clk) statement, and there’s the old style clk’event and clk = ‘1’ method.
The two if-statements do the same thing once the code is on the FPGA. They postulate that whatever is inside of the if-statement happens on the rising edge of the trigger signal,
This tutorial shows how to install the Lattice iCEcube2 FPGA design software on Ubuntu 20.04. Instead of the Lattice Diamond Programmer, we will use the alternative programmer from Project IceStorm that works flawlessly on Ubuntu Linux.
The Lattice iCEcube2 FPGA design software only works on Red Hat-based Linux distributions out of the box. Fortunately, we can make it run perfectly on Ubuntu Linux by installing dependencies and making a few changes to our system.
I’ve noticed that many of the gadgets that I’ve bought the last couple of years have shifted away from LED blinking to led breathing. Most electronic gizmos contain a status LED whose behavior gives away indications of what’s going on inside of the device.
My electric toothbrush flashes an LED when it’s time to recharge it, and my mobile phone uses the LED to call my attention for a wide variety of reasons.
Pulse-width modulation (PWM) is an efficient way to control analog electronics from purely digital FPGA pins. Instead of attempting to regulate the analog voltage, PWM rapidly switches on and off the supply current at full power to the analog device. This method gives us precise control over the moving average of energy provided to the consumer device.
Examples of use cases that are good candidates for PWM are audio modulation (speakers), light intensity control (lamps or LEDs),
The ModelSim version that comes with Intel Quartus Prime Lite Edition is a good alternative if you want to try out VHDL simulation on your home computer. The software is available for both Windows and Linux, but Intel only supports Red Hat-based distros like CentOS Linux.
Fortunately, you are just a few hacks away from ModelSim working nicely on your Ubuntu box.
One question that I’ve debated many times over the years is whether it’s OK to use variables for registers in VHDL. It’s safe to say that newbies are more likely to do it than experienced VHDL designers. But is there any merit to that, or is it just a matter of preference?
In this blog post, I will try to shed some light on the issue so that you can make an informed decision about using this design practice.
Many people turn to me for advice regarding their FPGA projects. Often, my answer is not what they expected: have you considered using a microcontroller instead of an FPGA?
I’m running VHDLwhiz, the website dedicated to FPGA design using VHDL. My life revolves around FPGAs, and I’m the biggest proponent of VHDL there is. Why would I say such a thing?
It’s because, for some tasks, an FPGA is overkill.
VHDL has a built-in pseudo-random generator, but it can only generate floating-point numbers between 0 and 1. Fortunately, you can derive from this any other kind of random data format you should need. Continue reading this article to find out how to produce real or integer values of any range, as well as random std_logic_vector sequences and time values.
